There are maskable and non-maskable interrupt signals. Non-maskable interrupt signals have the highest priority and are authorized to interrupt the execution of maskable interrupt routines to achieve an immediate start of the non-maskable interrupt routine. It is known from JP 3-229 332 A in: Patent Abstracts of Japan, Section P, No. 1296, Vol. 16, No. 9, page 90, to dispose in a signal path between a circuit component delivering a non-maskable interrupt signal and a CPU responsive thereto, a controllable interrupt signal passage circuit which, in response to an output signal of a control signal source, can be controlled to a state permitting passage of the non-maskable interrupt signal or a state blocking the non-maskable interrupt signal. To this end, there is provided an AND circuit, with one input thereof being fed with the non-maskable interrupt signal and with the other input thereof being connected to an output of a flipflop adapted to be fed with a control signal determining the switching state of the flip-flop. Depending on the switching state of the flipflop, the non-maskable interrupt signal is thus either allowed to pass to the CPU or blocked. The control signal blocking such passage is supplied to the flipflop during loading of a starting program. As long as the control signal controls for passage of the non-maskable interrupt signal, the non-maskable interrupt signal reaches the CPU.
Too frequent occurrence of non-maskable interrupt signals, for example due to interferences on the circuit board on which there is a line for non-maskable interrupt signals, can result in erroneous behavior of the program-controlled system. When mainly the non-maskable interrupt routine is active, there is probably too little calculating power left for other tasks of complex systems.